Live Demonstration: 5-bit signed SRAM-based DNN CIM for Image Recognition
Ó. Pereira-Rial, D. García-Lesta, Lorenzo Vaquero, P. López, Víctor M. Brea, D. Cabello
IEEE International Symposium on Circuits and Systems
A live mixed-signal compute-in-memory demonstration uses 5-bit signed SRAM weights and PWM-coded images for low-power DNN image recognition.
This live demonstration shows a mixed-signal compute-in-memory macro deep neural network integrated circuit in 180 nm CMOS technology for image recognition. Images are coded as pulse-width modulation signals, while DNN weights are stored as voltages in 6T-SRAM memories that drive current sources inside every multiplier. Multipliers are arranged within processing elements laid down in a 2D mesh suitable for image processing. The macro implements a lightweight CNN for digit recognition on MNIST, using an FPGA and tablet interface so visitors can draw digits and see the predicted probabilities. The power consumption per multiplier of the CIM macro is 0.22 uW, below state-of-the-art competitors following the same multiply-and-accumulate principle.
@inproceedings{pereirarial2024live,
author = {{\'{O}}. Pereira-Rial and
D. Garc{\'{\i}}a-Lesta and
Lorenzo Vaquero and
P. L{\'{o}}pez and
V. M. Brea and
D. Cabello},
title = {Live Demonstration: 5-bit signed {SRAM}-based {DNN} {CIM}
for Image Recognition},
booktitle = {{IEEE} Int. Symp. Circuits Syst. ({ISCAS})},
pages = {1-1},
year = {2024},
doi = {10.1109/ISCAS58744.2024.10558078}
}